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4.4.27. AArch32 Virtualization registers

Table 4.155 shows the Virtualization registers. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.155. Virtualization registers
NameCRnOp1CRmOp2ResetWidthDescription
VPIDRc04c000x410FD03432-bit

Virtualization Processor ID Register

VMPIDR   5-[a]32-bitVirtualization Multiprocessor ID Register
HSCTLRc14c000x30C5083832-bit

Hyp System Control Register

HACTLR  1UNK Hyp Auxiliary Control Register
HCR  c100x0000000032-bit

Hyp Configuration Register

HDCR   10x0000000632-bit

Hyp Debug Control Register

HCPTR   20x000033FF[b]32-bit

Hyp Architectural Feature Trap Register

HSTR   30x0000000032-bit

Hypervisor System Trap Register

HTCRc24c02UNK32-bit

Hyp Translation Control Register

VTCR  c12UNK32-bit

Virtualization Translation Control Register

HTTBR-4c2-UNK64-bit

Hyp Translation Table Base Register

VTTBR-6c2-UNK64-bit

Virtualization Translation Table Base Register

HADFSRc54c100x0000000032-bit

Hyp Auxiliary Data Fault Status Syndrome Register

HAIFSR   10x0000000032-bit

Hyp Auxiliary Instruction Fault Status Syndrome Register

HSR  c20

UNK

32-bitHyp Syndrome Register
HDFARc64c00UNK32-bit

Hyp Data Fault Address Register

HIFAR   2UNK32-bit

Hyp Instruction Fault Address Register

HPFAR   4UNK32-bit

Hyp IPA Fault Address Register

HMAIR0c104c20UNK32-bit

Hyp Memory Attribute Indirection Register 0

HMAIR1 1UNK32-bit

Hyp Memory Attribute Indirection Register 1

HAMAIR0c300x0000000032-bitHyp Auxiliary Memory Attribute Indirection Register 0
HAMAIR1 10x0000000032-bitHyp Auxiliary Memory Attribute Indirection Register 1
HVBARc124c00UNK32-bit

Hyp Vector Base Address Register

[a] The reset value is the value of the Multiprocessor Affinity Register.

[b] The reset value depends on the FPU and NEON configuration. If Advanced SIMD and Floating-point are implemented, the reset value is 0x000033FF. If Advanced SIMD and Floating-point are not implemented, the reset value is 0x0000BFFF.


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