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4.4.1. c0 registers

Table 4.130 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c0.

Table 4.130. c0 register summary
CRnOp1CRmOp2NameResetDescription
c00c00MIDR0x410FD034

Main ID Register

1CTR0x84448004

Cache Type Register

2TCMTR0x00000000

TCM Type Register

3TLBTR0x00000000

TLB Type Register

4, 7MIDR0x410FD034

Aliases of Main ID Register, Main ID Register

5MPIDR-[a]

Multiprocessor Affinity Register

6REVIDR0x00000000Revision ID Register
c10ID_PFR00x00000131

Processor Feature Register 0

1ID_PFR10x10011011[b]

Processor Feature Register 1

2ID_DFR00x03010066

Debug Feature Register 0

3ID_AFR00x00000000Auxiliary Feature Register 0
4ID_MMFR00x10201105

Memory Model Feature Register 0

5ID_MMFR10x40000000

Memory Model Feature Register 1

6ID_MMFR20x01260000

Memory Model Feature Register 2

7ID_MMFR30x02102211

Memory Model Feature Register 3

c20ID_ISAR00x02101110

Instruction Set Attribute Register 0

1ID_ISAR10x13112111

Instruction Set Attribute Register 1

2ID_ISAR20x21232042

Instruction Set Attribute Register 2

3ID_ISAR30x01112131

Instruction Set Attribute Register 3

0c24ID_ISAR40x00011142

Instruction Set Attribute Register 4

5ID_ISAR50x00011121[c]

Instruction Set Attribute Register 5

1c00CCSIDR-

Cache Size ID Register

1CLIDR0x0A200023[d]

Cache Level ID Register

7AIDR0x00000000

Auxiliary ID Register

2c00CSSELR0x00000000Cache Size Selection Register
4c00VPIDR0x410FD034

Virtualization Processor ID Register

5VMPIDR-[e]Virtualization Multiprocessor ID Register

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements.

[b] Bits [31:28] are 0x1 if the GIC CPU interface is enabled, and 0x0 otherwise.

[c] ID_ISAR5 has the value 0x00010001 if the Cryptography Extension is not implemented and enabled.

[d] The value is 0x09200003 if the L2 cache is not implemented.

[e] The reset value is the value of the Multiprocessor Affinity Register.


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