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4.4.2. c1 registers

Table 4.131 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c1.

Table 4.131. c1 register summary
CRnOp1CRmOp2NameResetDescription
c10c00SCTLR0x00C50838[a]

System Control Register

1ACTLR

0x00000000

Auxiliary Control Register

2CPACR0x00000000

Architectural Feature Access Control Register

c10SCR0x00000000

Secure Configuration Register

1SDER0x00000000

Secure Debug Enable Register

2NSACR

0x00000000[b]

Non-Secure Access Control Register

c31SDCR0x00000000Secure Debug Control Register
4c00HSCTLR0x03C50838

Hyp System Control Register

1HACTLR0x00000000Auxiliary Control Register, EL2
c10HCR0x00000000

Hyp Configuration Register

1HDCR0x00000006

Hyp Debug Control Register

2HCPTR0x000033FF[c]

Hyp Architectural Feature Trap Register

3HSTR0x00000000

Hyp System Trap Register

4HCR20x00000000Hyp Configuration Register 2
7HACR0x00000000Hyp Architectural Feature Trap Register

[a] The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.130 assumes these signals are set to LOW.

[b] If EL3 is AArch64 then the NSACR reads as 0x00000C00.

[c] The reset value depends on the FPU and NEON configuration. If Advanced SIMD and Floating-point are implemented, the reset value is 0x000033FF. If Advanced SIMD and Floating-point are not implemented, the reset value is 0x0000BFFF.


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