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Table 4.141 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c10.
| CRn | Op1 | CRm | Op2 | Name | Reset | Description |
|---|---|---|---|---|---|---|
| c10 | 0 | c2 | 0 | PRRR | UNK | |
| 0 | MAIR0 | UNK | Memory Attribute Indirection Registers 0 and 1 | |||
| 1 | NMRR | UNK | Normal Memory Remap Register | |||
| 1 | MAIR1 | UNK | Memory Attribute Indirection Registers 0 and 1 | |||
| c3 | 0 | AMAIR0 | 0x00000000 | Auxiliary Memory Attribute Indirection Register 0 | ||
| 1 | AMAIR1 | 0x00000000 | Auxiliary Memory Attribute Indirection Register 1 | |||
| 4 | c2 | 0 | HMAIR0 | UNK | Hyp Memory Attribute Indirection Register 0[a] | |
| 1 | HMAIR1 | UNK | Hyp Memory Attribute Indirection Register 1[a] | |||
| c3 | 0 | HAMAIR0 | 0x00000000 | Hyp Auxiliary Memory Attribute Indirection Register 0 | ||
| 1 | HAMAIR1 | 0x00000000 | Hyp Auxiliary Memory Attribute Indirection Register 1 | |||
[a] See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information. | ||||||