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4.4.17. c15 registers

Table 4.145 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c15.

Table 4.145. c15 register summary
Op1CRmOp2NameResetDescription
1c00L2ACTLR0x80000000[a]L2 Auxiliary Control Register
c30CBAR-[b]Configuration Base Address Register
3c00CDBGDR0UNKCache Debug Data Register 0, see Direct access to internal memory
1CDBGDR1UNKCache Debug Data Register 1, see Direct access to internal memory
2CDBGDR2UNKCache Debug Data Register 2, see Direct access to internal memory
3CDBGDR3 UNKCache Debug Data Register 3, see Direct access to internal memory
c20CDBGDCTUNKCache Debug Data Cache Tag Read Operation Register, see Direct access to internal memory
1CDBGICT UNKCache Debug Instruction Cache Tag Read Operation Register, see Direct access to internal memory
c40CDBGDCD UNKCache Debug Cache Debug Data Cache Data Read Operation Register, see Direct access to internal memory
1CDBGICDUNKCache Debug Instruction Cache Data Read Operation Register, see Direct access to internal memory
2CDBGTDUNKCache Debug TLB Data Read Operation Register, see Direct access to internal memory

[a] This is the reset value for an ACE interface. For a CHI interface the reset value is 0x 80004008.

[b] The reset value depends on the processor configuration.


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