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4.4.11. c9 registers

Table 4.140 shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c9. See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4.140. c9 register summary
CRnOp1CRmOp2NameResetDescription
c90c120PMCR0x41033000

Performance Monitors Control Register

1PMNCNTENSETUNK

Performance Monitors Count Enable Set Register

2PMNCNTENCLRUNK

Performance Monitors Count Enable Clear Register

3PMOVSRUNK

Performance Monitor Overflow Flag Status Clear Register

4PMSWINCUNK

Performance Monitors Software Increment Register

5PMSELRUNK

Performance Monitors Event Counter Selection Register

6PMCEID00x67FFBFFF[a]Performance Monitors Common Event Identification Register 0
7PMCEID10x00000000Performance Monitors Common Event Identification Register 1
c130PMCCNTRUNK

Performance Monitors Cycle Counter

1

PMXEVTYPER

UNKPerformance Monitors Selected Event Type and Filter Register
2PMXEVCNTRUNKPerformance Monitors Selected Event Counter Register
c140PMUSERENR0x00000000

Performance Monitors User Enable Register

1PMINTENSETUNKPerformance Monitors Interrupt Enable Set Register
2PMINTENCLRUNK

Performance Monitors Interrupt Enable Clear Register

3PMOVSSETUNK

Performance Monitor Overflow Flag Status Set Register

1c02L2CTLR-[b]

L2 Control Register

3L2ECTLR0x00000000L2 Extended Control Register

[a] The reset value is 0x663FBFFF if L2 cache is not implemented.

[b] The reset value depends on the processor configuration.


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