The ID_ISAR2_EL1 characteristics are:
Provides information about the instruction sets implemented by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_ISAR2_EL1 is architecturally mapped to AArch32 register ID_ISAR2. See Instruction Set Attribute Register 2.
ID_ISAR2_EL1 is a 32-bit register.
Figure 4.13 shows the ID_ISAR2_EL1 bit assignments.
Table 4.42 shows the ID_ISAR2_EL1 bit assignments.
Indicates the implemented Reversal instructions:
Indicates the implemented A and R profile instructions to manipulate the PSR:
The exception return forms of the data-processing instructions are:
Indicates the implemented advanced unsigned Multiply instructions:
Indicates the implemented advanced signed Multiply instructions.
Indicates the implemented additional Multiply instructions:
Indicates the support for interruptible multi-access instructions:
Indicates the implemented memory hint instructions:
Indicates the implemented additional load/store instructions:
To access the ID_ISAR2_EL1:
MRS <Xt>, ID_ISAR2_EL1 ; Read ID_ISAR2_EL1 into Xt
Register access is encoded as follows: