The ID_AA64DFR0_EL1 characteristics are:
Provides top level information of the debug system in the AArch64 Execution state.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_AA64DFR0_EL1 is architecturally mapped to external register ID_AA64DFR0.
ID_AA64DFR0_EL1 is a 64-bit register.
Figure 4.18 shows the ID_AA64DFR0_EL1 bit assignments.
Table 4.52 shows the ID_AA64DFR0_EL1 bit assignments.
Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints:
The number of watchpoints minus 1:
The number of breakpoints minus 1:
Performance Monitors extension version.
Debug architecture version:
To access the ID_AA64DFR0_EL1:
MRS <Xt>, ID_AA64DFR0_EL1 ; Read ID_AA64DFR0_EL1 into Xt
Register access is encoded as follows: