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4.3.65. L2 Extended Control Register

The L2ECTLR_EL1 characteristics are:

Purpose

Provides additional implementation defined control options for the L2 memory system. This register is used for dynamically changing, but implementation specific, control bits.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RWRWRWRWRW

The L2ECTLR_EL1 can be written dynamically.

Configurations

L2ECTLR_EL1 is architecturally mapped to the AArch32 L2ECTLR register. See L2 Extended Control Register.

There is one copy of this register that is used in both Secure and Non-secure states.

There is one L2ECTLR_EL1 for the Cortex-A53 processor.

Attributes

L2ECTLR_EL1 is a 32-bit register.

Figure 4.59 shows the L2ECTLR_EL1 bit assignments.

Figure 4.59. L2ECTLR_EL1 bit assignments

Figure 4.59. L2ECTLR_EL1 bit assignments

Table 4.108 shows the L2ECTLR_EL1 bit assignments.

Table 4.108. L2ECTLR_EL1 bit assignments
BitsNameFunction
[31]-

Reserved, res0.

[30]L2 internal asynchronous error

L2 internal asynchronous error caused by L2 RAM double-bit ECC error. The possible values are:

0

No pending asynchronous error. This is the reset value.

1

An asynchronous error has occurred.

A write of 0 clears this bit and drives nINTERRIRQ HIGH. A write of 1 is ignored.

[29]AXI or CHI asynchronous error

AXI or CHI asynchronous error indication. The possible values are:

0

No pending asynchronous error.

1

An asynchronous error has occurred.

A write of 0 clears this bit and drives nEXTERRIRQ HIGH. A write of 1 is ignored.

[28:3]-

Reserved, res0.

[2:0]L2 dynamic retention control

L2 dynamic retention control. The possible values are:

0b000

L2 dynamic retention disabled. This is the reset value.

0b001

2 Generic Timer ticks required before retention entry.

0b010

8 Generic Timer ticks required before retention entry.

0b011

32 Generic Timer ticks required before retention entry.

0b100

64 Generic Timer ticks required before retention entry.

0b101

128 Generic Timer ticks required before retention entry.

0b110

256 Generic Timer ticks required before retention entry.

0b111

512 Generic Timer ticks required before retention entry.

Note

Software must not rely on retention state entry when the system counter is in low-power modes where CNTVALUEB increments are greater than 1. Entry to retention state relies on the system counter increments being +1.


To access the L2ECTLR_EL1:

MRS Rt, S3_1_C11_C0_3; Read L2ECTLR_EL1 into Rt
MSR S3_1_C11_C0_3, Rt; Write Rt to L2ECTLR_EL1