The L2ECTLR_EL1 characteristics are:
Provides additional implementation defined control options for the L2 memory system. This register is used for dynamically changing, but implementation specific, control bits.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
The L2ECTLR_EL1 can be written dynamically.
L2ECTLR_EL1 is architecturally mapped to the AArch32 L2ECTLR register. See L2 Extended Control Register.
There is one copy of this register that is used in both Secure and Non-secure states.
There is one L2ECTLR_EL1 for the Cortex-A53 processor.
L2ECTLR_EL1 is a 32-bit register.
Figure 4.59 shows the L2ECTLR_EL1 bit assignments.
Table 4.108 shows the L2ECTLR_EL1 bit assignments.
|||L2 internal asynchronous error|
L2 internal asynchronous error caused by L2 RAM double-bit ECC error. The possible values are:
A write of
|||AXI or CHI asynchronous error|
AXI or CHI asynchronous error indication. The possible values are:
A write of
|[2:0]||L2 dynamic retention control|
L2 dynamic retention control. The possible values are:
Software must not rely on retention state entry when the system counter is in low-power modes where CNTVALUEB increments are greater than 1. Entry to retention state relies on the system counter increments being +1.
To access the L2ECTLR_EL1:
MRS Rt, S3_1_C11_C0_3; Read L2ECTLR_EL1 into Rt MSR S3_1_C11_C0_3, Rt; Write Rt to L2ECTLR_EL1