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4.3.44. Translation Table Base Register 0, EL1

The TTBR0_EL1 characteristics are:


Holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses from modes other than Hyp mode.

Usage constraints

This register is accessible as follows:








(SCR.NS = 1)


(SCR.NS = 0)


Any of the fields in this register are permitted to be cached in a TLB.


TTBR0_EL1 is architecturally mapped to AArch32 register TTBR0. See Translation Table Base Register 0.


TTBR0_EL1 is 64-bit register.

Figure 4.40 shows the TTBR0_EL1 bit assignments.

Figure 4.40. TTBR0_EL1 bit assignments

Figure 4.40. TTBR0_EL1 bit assignments

Table 4.84 shows the TTBR0_EL1 bit assignments.

Table 4.84. TTBR0_EL1 bit assignments

An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID.


Translation table base address, bits[47:x]. Bits [x-1:0] are res0.

x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation granule size.

For instructions on how to calculate it, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile

The value of x determines the required alignment of the translation table, that must be aligned to 2x bytes.

If bits [x-1:0] are not all zero, this is a misaligned Translation Table Base Address. Its effects are constrained unpredictable, where bits [x-1:0] are treated as if all the bits are zero. The value read back from those bits is the value written.

To access the TTBR0_EL1:

MRS <Xt>, TTBR0_EL1 ; Read TTBR0_EL1 into Xt
MSR TTBR0_EL1, <Xt> ; Write Xt to TTBR0_EL1