The VBAR_EL1 characteristics are:
Holds the exception base address for any exception that is taken to EL1.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
The VBAR_EL1[31:0] is architecturally mapped to the Non-secure AArch32 VBAR register. See Vector Base Address Register.
VBAR_EL1 is a 64-bit register.
Figure 4.65 shows the VBAR_EL1 bit assignments.
Table 4.116 shows the VBAR_EL1 bit assignments.
|[63:11]||Vector base address|
Base address of the exception vectors for exceptions taken in this exception level.
To access the VBAR_EL1:
MRS <Xt>, VBAR_EL1 ; Read VBAR_EL1 into Xt MSR VBAR_EL1, <Xt> ; Write Xt to VBAR_EL1