The VTCR_EL2 characteristics are:
Controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1, and holds cacheability and shareability information for the accesses.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - RW RW RW
Any of the bits in VTCR_EL2 are permitted to be cached in a TLB.
VTCR_EL2 is architecturally mapped to AArch32 register VTCR. See Virtualization Translation Control Register.
VTCR_EL2 is a 32-bit register.
Figure 4.46 shows the VTCR_EL2 bit assignments.
Table 4.90 shows the VTCR_EL2 bit assignments.
Physical Address Size. The possible values are:
All other values are reserved.
Granule size for the corresponding VTTBR_EL2.
All other values are not supported.
Shareability attribute for memory associated with translation table walks using VTTBR_EL2.
Outer cacheability attribute for memory associated with translation table walks using VTTBR_EL2.
Inner cacheability attribute for memory associated with translation table walks using VTTBR_EL2.
|[7:6]||SL0||Starting level of the VTCR_EL2 addressed region.|
The size offset of the memory region addressed by VTTBR_EL2. The region size is 2(64-T0SZ) bytes.
To access the VTCR_EL2:
MRS <Xt>, VTCR_EL2 ; Read VTCR_EL2 into Xt MSR VTCR_EL2, <Xt> ; Write Xt to VTCR_EL2