Table 4.5 shows the System instructions for cache and maintenance operations in AArch64 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.
Instruction cache invalidate all to PoU[a] Inner Shareable
Instruction cache invalidate all to PoU
Instruction cache invalidate by virtual address (VA) to PoU
|Data cache invalidate by VA to PoC[b]|
Data cache invalidate by set/way
Data cache clean by set/way
Data cache clean and invalidate by set/way
|Data cache zero by VA|
Data cache clean by VA to PoC
Data cache clean by VA to PoU
Data cache clean and invalidate by VA to PoC
[a] PoU = Point of Unification. PoU is set by the BROADCASTINNER signal and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.
[b] PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.