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4.2.11. AArch64 secure registers

Table 4.12 shows the secure registers in AArch64 state.

Table 4.12. AArch64 security registers

Secure Configuration Register


Secure Debug Enable Register

CPTR_EL3RW0x000033FF[a]32Architectural Feature Trap Register, EL3

Monitor Debug Configuration Register, EL3

AFSR0_EL3RW0x0000000032Auxiliary Fault Status Register 0, EL1, EL2 and EL3
AFSR1_EL3RW0x0000000032Auxiliary Fault Status Register 1, EL1, EL2 and EL3
VBAR_EL3RWUNK64Vector Base Address Register, EL3

[a] Reset value is 0x000033FF if Advanced SIMD and Floating point are implemented, 0x000037FF otherwise.