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13.8.5. Auxiliary Control Register

The TRCAUXCTLR characteristics are:

Purpose

The function of this register is to provide implementation defined configuration and control options.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.7 shows the TRCAUXCTLR bit assignments.

Figure 13.7. TRCAUXCTLR bit assignments

Figure 13.7. TRCAUXCTLR bit assignments

Table 13.8 shows the TRCAUXCTLR bit assignments.

Table 13.8. TRCAUXCTLR bit assignments
BitsNameFunction
[31:8]-Reserved, res0.
[7]

COREIFEN

Keep core interface enabled regardless of trace enable register state. The possible values are:

0

Core interface enabled is set by trace enable register state.

1

Enable core interface, regardless of trace enable register state.

[6]-

Reserved, res0.

[5]

AUTHNOFLUSH

Do not flush trace on de-assertion of authentication inputs. The possible values are:

0

ETM trace unit FIFO is flushed and ETM trace unit enters idle state when DBGEN or NIDEN is LOW.

1

ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state when DBGEN or NIDEN is LOW.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

[4]

TSNODELAY

Do not delay timestamp insertion based on FIFO depth. The possible values are:

0

Timestamp packets are inserted into FIFO only when trace activity is LOW.

1

Timestamp packets are inserted into FIFO irrespective of trace activity.

[3]

SYNCDELAY

Delay periodic synchronization if FIFO is more than half-full. The possible values are:

0

SYNC packets are inserted into FIFO only when trace activity is low.

1

SYNC packets are inserted into FIFO irrespective of trace activity.

[2]

OVFLW

Force an overflow if synchronization is not completed when second synchronization becomes due. The possible values are:

0

No FIFO overflow when SYNC packets are delayed.

1

Forces FIFO overflow when SYNC packets are delayed.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

[1]

IDLEACK

Force idle-drain acknowledge high, CPU does not wait for trace to drain before entering WFX state. The possible values are:

0

ETM trace unit idle acknowledge is asserted only when the ETM trace unit is in idle state.

1

ETM trace unit idle acknowledge is asserted irrespective of the ETM trace unit idle state.

When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.

[0]

AFREADY

Always respond to AFREADY immediately. Does not have any interaction with FIFO draining, even in WFI state. The possible values are:

0

ETM trace unit AFREADYM output is asserted only when the ETM trace unit is in idle state or when all the trace bytes in FIFO before a flush request are output.

1

ETM trace unit AFREADYM output is always asserted HIGH. When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.


The TRCAUXCTLR can be accessed through the external debug interface, offset 0x018.

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