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13.8.34. ID Register 3

The TRCIDR3 characteristics are:

Purpose

Indicates:

  • Whether TRCVICTLR is supported.

  • The number of cores available for tracing.

  • If an exception level supports instruction tracing.

  • The minimum threshold value for instruction trace cycle counting.

  • Whether the synchronization period is fixed.

  • Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and supports stall control of the processor.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 13.3.

Figure 13.36 shows the TRCIDR3 bit assignments.

Figure 13.36. TRCIDR3 bit assignments

Figure 13.36. TRCIDR3 bit assignments

Table 13.37 shows the TRCIDR3 bit assignments.

Table 13.37. TRCIDR3 bit assignments
BitsNameFunction
[31]NOOVERFLOW

Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:

0

TRCSTALLCTLR.NOOVERFLOW is not implemented.

[30:28]NUMPROC

Indicates the number of cores available for tracing:

0b000

The trace unit can trace one processor, ETM trace unit sharing not supported.

[27]SYSSTALL

Indicates whether stall control is implemented:

1

The system supports processor stall control.

[26]STALLCTL

Indicates whether TRCSTALLCTLR is implemented:

1

TRCSTALLCTLR is implemented.

This field is used in conjunction with SYSSTALL.

[25]SYNCPR

Indicates whether there is a fixed synchronization period:

0

TRCSYNCPR is read-write so software can change the synchronization period.

[24]TRCERR

Indicates whether TRCVICTLR.TRCERR is implemented:

1

TRCVICTLR.TRCERR is implemented.

[23:20]EXLEVEL_NS

Each bit controls whether instruction tracing in Non-secure state is implemented for the corresponding exception level:

0b0111

Instruction tracing is implemented for Non-secure EL0, EL1 and EL2 exception levels.

[19:16]EXLEVEL_S

Each bit controls whether instruction tracing in Secure state is implemented for the corresponding exception level:

0b1011

Instruction tracing is implemented for Secure EL0, EL1 and EL3 exception levels.

[15:12]-

Reserved, res0.

[11:0]CCITMIN

The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:

0x004

Instruction trace cycle counting minimum threshold is 4.


The TRCIDR3 can be accessed through the external debug interface, offset 0x1EC.

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