The TRCLAR characteristics are:
- Purpose
Controls access to registers using the memory-mapped interface, when PADDRDBG31 is LOW.
When the software lock is set, write accesses using the memory-mapped interface to all ETM trace unit registers are ignored, except for write accesses to the TRCLAR.
When the software lock is set, read accesses of TRCPDSR do not change the TRCPDSR.STICKYPD bit. Read accesses of all other registers are not affected.
- Usage constraints
Accessible only from the external debug interface.
- Configurations
Available in all configurations.
- Attributes
See the register summary in Table 13.3.
Figure 13.59 shows the TRCLAR bit assignments.
Table 13.61 shows the TRCLAR bit assignments.
| Bits | Name | Function |
|---|---|---|
| [31:0] | KEY | Software lock key value:
All other write values set the software lock. |
The TRCLAR can be accessed through the external debug interface
interface, offset 0xFB0.