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13.7. ETM register summary

This section summarizes the ETM trace unit registers. For full descriptions of the ETM trace unit registers, see:

  • ETM register descriptions, for the implementation defined registers and the Arm® ETM Architecture Specification, ETMv4, for the other registers.


In Table 13.3, access type is described as follows:


Read and write.


Read only.


Write only.

Table 13.3 lists all of the ETM trace unit registers.

All ETM trace unit registers are 32 bits wide. The description of each register includes its offset from a base address. The base address is defined by the system integrator when placing the ETM trace unit in the Debug-APB memory map.

Table 13.3. ETM trace unit register summary

Programming Control Register

TRCSTATRROStatus Register
TRCCONFIGRRWTrace Configuration Register
TRCAUXCTLRRWAuxiliary Control Register
TRCEVENTCTL0RRWEvent Control 0 Register
TRCEVENTCTL1RRWEvent Control 1 Register
TRCSTALLCTLRRWStall Control Register
TRCTSCTLRRWGlobal Timestamp Control Register
TRCSYNCPRRW Synchronization Period Register
TRCCCCTLRRWCycle Count Control Register
TRCBBCTLRRWBranch Broadcast Control Register
TRCVICTLRRWViewInst Main Control Register
TRCVIIECTLRRWViewInst Include-Exclude Control Register
TRCVISSCTLRRWViewInst Start-Stop Control Register
TRCSEQEVR0RWSequencer State Transition Control Registers 0-2
TRCSEQEVR1RWSequencer State Transition Control Registers 0-2
TRCSEQEVR2RWSequencer State Transition Control Registers 0-2
TRCSEQRSTEVRRWSequencer Reset Control Register
TRCSEQSTRRWSequencer State Register
TRCEXTINSELRRWExternal Input Select Register
TRCCNTRLDVR0RWCounter Reload Value Registers 0-1
TRCCNTRLDVR1RWCounter Reload Value Registers 0-1
TRCCNTCTLR0RWCounter Control Register 0
TRCCNTCTLR1RWCounter Control Register 1
TRCCNTVR0RWCounter Value Registers 0-1
TRCCNTVR1RWCounter Value Registers 0-1
TRCIDR8ROID Register 8
TRCIDR9ROID Register 9
TRCIDR10ROID Register 10
TRCIDR11ROID Register 11
TRCIDR12ROID Register 12
TRCIDR13ROID Register 13
TCRIMSPEC0RWImplementation Specific Register 0
TRCIDR0ROID Register 0
TRCIDR1ROID Register 1
TRCIDR2ROID Register 2
TRCIDR3ROID Register 3
TRCIDR4ROID Register 4
TRCIDR5ROID Register 5
TRCRSCTLRnRWResource Selection Control Registers 2-16, n is 2, 15
TRCSSCCR0RWSingle-Shot Comparator Control Register 0
TRCSSCSR0RW, ROSingle-Shot Comparator Status Register 0
TRCOSLARWOOS Lock Access Register
TRCOSLSRROOS Lock Status Register
TRCPDCRRWPower Down Control Register
TRCPDSRROPower Down Status Register
TRCACVRnRWAddress Comparator Value Registers 0-7
TRCACATRnRWAddress Comparator Access Type Registers 0-7
TRCCIDCVR0RWContext ID Comparator Value Register 0
TRCVMIDCVR0RWVMID Comparator Value Register 0
TRCCIDCCTLR0RWContext ID Comparator Control Register 0
TRCITATBIDRRWIntegration ATB Identification Register
TRCITIDATARWOIntegration Instruction ATB Data Register
TRCITIATBINRROIntegration Instruction ATB In Register
TRCITIATBOUTRWOIntegration Instruction ATB Out Register
TRCITCTRLRWIntegration Mode Control Register
TRCCLAIMSETRWClaim Tag Set Register
TRCCLAIMCLRRWClaim Tag Clear Register
TRCDEVAFF0RODevice Affinity Register 0
TRCDEVAFF1RODevice Affinity Register 1
TRCLARWOSoftware Lock Access Register
TRCLSRROSoftware Lock Status Register
TRCAUTHSTATUSROAuthentication Status Register
TRCDEVARCHRODevice Architecture Register
TRCDEVIDRODevice ID Register
TRCDEVTYPERODevice Type Register
TRCPIDR4ROPeripheral Identification Register 4
TRCPIDR5ROPeripheral Identification Register 5-7
TRCPIDR0ROPeripheral Identification Register 0
TRCPIDR1ROPeripheral Identification Register 1
TRCPIDR2ROPeripheral Identification Register 2
TRCPIDR3ROPeripheral Identification Register 3
TRCCIDR0ROComponent Identification Register 0
TRCCIDR1ROComponent Identification Register 1
TRCCIDR2ROComponent Identification Register 2
TRCCIDR3ROComponent Identification Register 3