The Translation Lookaside Buffer (TLB) contains the main TLB and handles all translation table walk operations for the processor. TLB entries are stored inside a 512-entry, 4-way set-associative RAM.
If the cache protection configuration is implemented, the TLB RAMs are protected by parity bits. The parity bits enable any single-bit error to be detected. If an error is detected, the entry is flushed and fetched again.
See Chapter 6 Level 1 Memory System for more information.