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2.3.3. Resets

The Cortex-A53 processor has the following active-LOW reset input signals:

nCPUPORESET[CN:0]

Where CN is the number of cores minus one.

These primary, Cold reset signals initialize all resettable registers in the corresponding core, including debug registers and ETM registers.

nCORERESET[CN:0]

These primary reset signals initialize all resettable registers in the corresponding core, not including debug registers and ETM registers.

nPRESETDBG

This single, cluster-wide signal resets the integrated CoreSight components that connect to the external PCLK domain, such as debug logic.

nL2RESET

This single, cluster-wide signal resets all resettable registers in the L2 memory system and the logic in the SCU.

nMBISTRESET

An external MBIST controller can use this signal to reset the entire SoC. The nMBISTRESET signal resets all resettable registers in the cluster, for entry into, and exit from, MBIST mode.

All of these resets can be asynchronously:

  • Asserted, HIGH to LOW.

  • Deasserted, LOW to HIGH.

Reset synchronization logic inside the Cortex-A53 processor ensures that reset deassertion is synchronous for all resettable registers. The processor clock is not required for reset assertion, but the processor clock must be present for reset deassertion to ensure reset synchronization.

In general, you only have to hold reset signals active for three processor clock cycles for the reset to take effect. However, you must hold the reset signal LOW until the power returns and the unit or processor is ready for the reset to take effect if:

  • The Advanced SIMD and floating-point unit of a core undergoing a reset is in retention state.

  • A core that is being reset is in retention state.

This is the responsibility of the system implementer, because the time taken for retention exit and the behavior of the power controller varies by partner and by implementation.

Table 2.1 describes the valid reset signal combinations. All other combinations of reset signals are illegal. In the table, n designates the core that is reset.

Table 2.1. Valid reset combinations
Reset combinationSignalsValueDescription
Cluster Cold reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 0[a]

all = X[a]

0

0

1

All logic is held in reset.
Cluster Cold reset with debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 0[a]

all = X[a]

1

0

1

All cores are held in reset so they can be powered up. The L2 is held in reset, but must remain powered up. This enables external debug over power down for the cluster.

Individual core Cold reset with debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

[n] = 0[a]

[n] = X[a]

1

1

1

Individual core is held in reset, so that the core can be powered up. This enables external debug over power down for the core that is held in reset.
Individual core Warm reset with trace and debug active

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

[n] = 1

[n] = 0

1

1

1

Individual core is held in reset.
Debug logic reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

0

1

1

Cluster debug logic is held in reset.
MBIST reset

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

1

1

0

All logic is held in reset.
Normal state

nCPUPORESET[CN:0]

nCORERESET[CN:0]

nPRESETDBG

nL2RESET

nMBISTRESET

all = 1

all = 1

1

1

1

No logic is held in reset.

[a] For Cold reset, nCPUPORESET must be asserted. nCORERESET can be asserted, but is not required.


Warm reset

The Warm reset initializes all logic in the individual core apart from the Debug and ETM logic in the CLK domain. All breakpoints and watchpoints are retained during a Warm reset sequence.

The following figure shows the Warm reset sequence for the Cortex-A53 processor.

Figure 2.8. Warm reset timing

Figure 2.8. Warm reset timing

Individual core Warm reset initializes all logic in a single core apart from its Debug, ETM, breakpoint, and watchpoint logic. Breakpoints and watchpoints for that core are retained. You must apply the correct sequence before applying Warm reset to that core.

For individual processor Warm reset:

  • You must apply steps 1 to 6 in the core powerdown sequence, see Individual core shutdown mode, and wait until STANDBYWFI is asserted, indicating that the core is idle, before asserting nCORERESET for that core.

  • nCORERESET for that core must assert for at least 3 CLK cycles.

  • nL2RESET must not assert while any individual core is active.

  • nPRESETDBG must not assert while any individual core is actively being debugged in normal operating mode.

Note

If core dynamic retention using the CPU Q-channel interface is used, the core must be in quiescent state with STANDBYWFI asserted and CPUQREQn, CPUQACCEPTn, and CPUQACCEPT must be LOW before nCORERESET is applied.

WARMRSTREQ and DBGRSTREQ

The ARMv8-A architecture provides a mechanism to configure whether a processor uses AArch32 or AArch64 at EL3 as a result of a Warm reset. When the Reset Request bit in the RMR or RMR_EL3 register is set to 1, the processor asserts the WARMRSTREQ signal and the SoC reset controller can use this request to trigger a Warm reset of the core and change the register width state. The AA64 bit in the RMR or RMR_EL3 register selects the register width at the next Warm reset, at the highest Exception level, EL3.

See the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for information about the recommended code sequence to use, to request a Warm reset.

You must apply steps 1 to 6 in the core powerdown sequence, see Individual core shutdown mode, and wait until STANDBYWFI asserts indicating the processor is idle, before asserting nCORERESET for that core. nCORERESET must satisfy the timing requirements described in the Warm reset section.

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