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2.4.4. Communication to the Power Management Controller

Communication between the Cortex-A53 processor and the system power management controller can be performed using one or both of the:


The STANDBYWFI[n] signal indicates when an individual core is in idle and low power state. The power management controller can remove power from an individual core when STANDBYWFI[n] is asserted. See Individual core shutdown mode for more information.

The STANDBYWFIL2 signal indicates when all individual cores and the L2 memory system are in idle and low-power state. A power management controller can remove power from the Cortex-A53 processor when STANDBYWFIL2 is asserted. See Cluster shutdown mode without system driven L2 flush and Cluster shutdown mode with system driven L2 flush for more information.


The Cortex-A53 processor includes a minimal L2 memory system in configurations without an L2 cache. Therefore, the power management controller must always wait for assertion of STANDBYWFIL2 before removing power from the Cortex-A53 processor.

Figure 2.12 shows how STANDBYWFI[3:0] and STANDBYWFIL2 correspond to individual cores and the Cortex-A53 processor.

Figure 2.12. STANDBYWFI[3:0] and STANDBYWFIL2 signals

Figure 2.12. STANDBYWFI[3:0] and STANDBYWFIL2


Q-channel is a clock and power controller to device interface, to manage device quiescence. The interface enables:

  • The controller to manage entry to, and exit from, a device quiescent state. Quiescence management is typically of, but not restricted to, clock gated, and power gated retention states, of the device or device partitions.

  • The capability to indicate a requirement for exit from the quiescent state. The associated signaling can contain contributions from other devices in the same power domain.

  • Optional device capability to deny a quiescence request.

  • Safe asynchronous interfacing across clock domains.


For more information, see the Low-Power Interface Specification: ARM® Q-Channel and P-Channel Interfaces.