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6.7.3. TLB RAM accesses

The Cortex-A53 processor unified TLB is built from a 4-way set-associative RAM based structure. To read the individual entries into the data registers software must write to the TLB Data Read Operation Register. Table 6.11 shows the write TLB Data Read Operation Register location encoding of Rd.

Table 6.11. TLB Data Read Operation Register location encoding
BitsDescription
[31:30] TLB way
[29:8] Unused
[7:0] TLB index

The TLB RAM contains the data for the main TLB, the walk cache, and the Intermediate Physical Address (IPA) cache RAMs. Table 6.12 shows the TLB indexes that determines the format of the TLB RAM accesses.

Table 6.12.  TLB RAM format
TLB index[7:0]Format
0-127Main TLB RAM, see Main TLB RAM
128-143Walk cache RAM, see Walk cache RAM
144-159IPA cache RAM, see IPA cache RAM
160-255Unused

Main TLB RAM

The main TLB RAM uses a 117-bit encoding:

Data Register 0[31:0]

TLB Descriptor[31:0].

Data Register 1[31:0]

TLB Descriptor[63:32].

Data Register 2[31:0]

TLB Descriptor[95:64].

Data Register 3[20:0]

TLB Descriptor[116:96].

Table 6.13 shows the data fields in the TLB descriptor.

Table 6.13.  Main TLB descriptor data fields
Bits NameDescription
[116:114]ParityECC inclusion is processor configuration dependent. If ECC is not configured, these bits are absent.
[113:112]S2 Level

The stage 2 level that gave this translation:

0b00

No stage 2 translation performed.

0b01

Level 1.

0b10

Level 2.

0b11

Level 3.

[111:109]S1 Size

The stage 1 size that gave this translation:

0b000

4KB.

0b001

64KB.

0b010

1MB.

0b011

2MB.

0b100

16MB.

0b101

512MB.

0b110

1GB.

[108:105]DomainValid only if the entry was fetched in VMSAv7 format.
[104:97]Memory Type and shareability

See Table 6.14.

[96]XS2Stage2 executable permissions.
[95]XS1NonusrNon user mode executable permissions.
[94]XS1UsrUser mode executable permissions.
[93:66]PAPhysical Address.
[65]NS, descriptorSecurity state allocated to memory region.
[64:63]HAPHypervisor access permissions.
[62:60]AP or HYPAccess permissions from stage-1 translation, or select EL2 or flag.
[59]nGNot global.
[58:56]Size

This field shows the encoding for the page size:

VMSAv8-32 Short-descriptor translation table format:

0b000

4KB.

0b010

64KB.

0b100

1MB.

0b110

16MB.

VMSAv8-32 Long-descriptor translation table format or VMSAv8-64 translation table format:

0b001

4KB.

0b011

64KB.

0b101

2MB.

0b111

512MB.

[55:40]ASIDAddress Space Identifier.
[39:32]VMIDVirtual Machine Identifier.
[31]NS (walk)Security state that the entry was fetched in.
[30:2]VAVirtual Address.
[1]Address Sign bitVA[48] sign bit.
[0]Valid

Valid bit:

0

Entry does not contain valid data.

1

Entry contains valid data.


Table 6.14 shows the main TLB memory types and shareability.

Table 6.14. Main TLB memory types and shareability
BitsMemory typeDescription
[7]Device0
Non-coherent, Outer WB
Non-coherent, Outer NC
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB1
[6]Device0
Non-coherent, Outer WB
Non-coherent, Outer NC1
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB

Transient:

0

Non-transient

1

Transient.

[5:4]Device

Stage 1 (Non-device) overridden by stage 2 (Device)

00

Not overridden

01

Overridden.

Non-coherent, Outer WB

Inner type:

10

NC.

11

WT.

Non-coherent, Outer NC11
Non-coherent, Outer WT

Inner type:

00

NC.

01

WB.

10

WT.

Coherent, Inner WB and Outer WB

Inner allocation hint:

00

NA.

01

WA.

10

RA.

11

WRA.

[3:2]Device

Device type:

00

nGnRnE.

01

nGnRE.

10

nGRE.

11

GRE.

Non-coherent, Outer WB

Outer allocation hint:

00

NA.

01

WA.

10

RA.

11

WRA.

Non-coherent, Outer WT
Coherent, Inner WB and Outer WB
Non-coherent, Outer NC

Inner type:

00

NC.

01

WB.

10

WT.

11

Unused.

[1:0]Device

Shareability

00

Non-shareable.

01

Unused.

10

Outer shareable.

11

Inner shareable.

Non-coherent, Outer WB
Non-coherent, Outer NC
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB

Walk cache RAM

The walk cache RAM uses 117-bit encoding when parity is enabled and 114-bit encoding when parity is disabled. Table 6.15 shows the data fields in the walk cache descriptor.

Table 6.15. Walk cache descriptor fields
Bits NameDescription
[116:114]ECCECC. If ECC is not configured, these bits are absent.
[113:84]PAPhysical Address of second, last translation level.
[83:60]VAVirtual address.
[59:56]-Reserved, must be zero.
[55:40]ASIDAddress Space Identifier.
[39:32]VMIDVirtual Machine Identifier.
[31]NS, walkSecurity state that the entry was fetched in.
[30:22]-Reserved, must be zero.
[21:18]DomainValid only if the entry was fetched in VMSAv7 format.
[17:16]Entry size

Memory size to which entry maps:

0b00

1MB.

0b01

2MB.

0b10

512MB.

0b11

Unused.

[15]NSTableCombined NSTable bits from first and second level stage 1 tables or NS descriptor (VMSA).
[14]PXNTableCombined PXNTable bits from stage1 descriptors up to last level.
[13]XNTableCombined XNTable bit from stage1 descriptors up to last level.
[12:11]APTableCombined APTable bits from stage1 descriptors up to last level.
[10]EL3Set if the entry was fetched in AArch64 EL3 mode.
[9]EL2Set if the entry was fetched in EL2 mode.
[8:1]AttrsPhysical attributes of the final level stage 1 table.
[0]Valid

Valid bit:

0

Entry does not contain valid data.

1

Entry contains valid data.


IPA cache RAM

The Intermediate Physical Address (IPA) cache RAM uses a 117-bit encoding when parity is enabled and 114-bit encoding when parity is disabled. Table 6.16 shows the data fields in the IPA cache descriptor.

Table 6.16. IPA cache descriptor fields
BitsNameDescription
[116:114]ECCECC. If ECC is not configured, these bits are absent.
[113:86]PAPhysical address.
[85:62]IPAUnused lower bits, page size dependent, must be zero.
[61:59]-Reserved, must be zero.
[58:56]Size

The size values are:

0b011

64KB.

0b101

2MB.

0b111

512MB.

[55:40]-Reserved, must be zero.
[39:32]VMIDVirtual Machine Identifier.
[31:11]-Reserved, must be zero.
[10]Contiguous Set if the pagewalk had contiguous bit set.
[9:6]MemattrsMemory attributes.
[5]XNExecute Never.
[4:3]HAPHypervisor access permissions.
[2:1]SHShareability.
[0]ValidThe entry contains valid data.