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7.3.8. AXI privilege information

AXI provides information about the privilege level of an access on the ARPROTM[0] and AWPROTM[0] signals. However, when accesses might be cached or merged together, the resulting transaction can have both privileged and unprivileged data combined. If this happens, the Cortex-A53 processor marks the transaction as privileged, even it if was initiated by an unprivileged process.

Table 7.10 shows Cortex-A53 processor exception levels and corresponding ARPROTM[0] and AWPROTM[0] values.

Table 7.10. Cortex-A53 MPCore mode and ARPROT and AWPROT values
Processor exception levelType of access

Value of ARPROT[0] and AWPROT[0]

EL0, EL1, EL2, EL3Cacheable read accessPrivileged access
EL0Device, or normal Non-cacheable read accessUnprivileged access
EL1, EL2, EL3Privileged access
EL0, EL1, EL2, EL3Cacheable write accessPrivileged access
EL0Device, nGnRnE, nGnRE, and nGRE write Unprivileged access
EL1, EL2, EL3Privileged access
EL0Normal Non-cacheable or Device GRE write, except for STREX, STREXB, STREXH, STREXD, STXR, STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP to shareable memoryPrivileged access
EL0Normal Non-cacheable write for STREX, STREXB, STREXH, STREXD, STXR STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP to shareable memoryUnprivileged access
EL1, EL2, EL3Normal Non-cacheable write Privileged access
EL0, EL1, EL2, EL3TLB page walk Privileged access