You copied the Doc URL to your clipboard.

7.4.3. CHI channel properties

Table 7.13 shows the properties of the CHI channels.

Table 7.13. CHI channel properties
Snoop acceptance capability10The SCU can accept and process a maximum of 10 snoop requests from the system.
DVM acceptance capability4

The SCU can accept and process a maximum of four DVM transactions from the system. Each of these four transactions can be a two part DVM message.


The interconnect must be configured to never send more than four DVM messages to a Cortex-A53 processor, otherwise the system might deadlock.

Snoop latencyHit

When there is a hit in L2 cache, the best case for response and data is 11 processor cycles. When there is a miss in L2 cache and a hit in L1 cache, the best case for response and data is 14 processor cycles.


Latencies can be higher if hazards occur or if there are not enough buffers to absorb requests.

MissBest case six processor cycles when the SCU duplicate tags and L2 tags indicate the miss.

The cluster takes a minimum of six cycles to provide a response to DVM packets.

Snoop filter SupportedThe cluster provides support for an external snoop filter in an interconnect. It indicates when clean lines are evicted from the processor by sending Evict transactions on the CHI write channel. However there are some cases where incorrect software can prevent an Evict transaction from being sent, therefore you must ensure that any external snoop filter is built to handle a capacity overflow that sends a back-invalidation to the processor if it runs out of storage.
Supported transactions-

All transactions described by the CHI protocol:

  • Are accepted on the CHI master interface from the system.

  • Can be produced on the CHI master interface except:

    • ReadClean.

    • WriteBackPtl.

    • WriteCleanPtl.

See the Arm® AMBA® 5 CHI Protocol Specification for more information about the CHI channel.