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7.4.2. CHI transfers

Table 7.12 shows the CHI transactions that can be generated, and some typical operations that might cause the transactions to be generated. This is not an exhaustive list of ways to generate each type of transaction, because there are many possibilities.

Table 7.12. CHI transactions
TransactionOperation
ReadNoSnpNon-cacheable loads or instruction fetches. Linefills of non-shareable cache lines into L1 or L2.
ReadOnceCacheable loads that are not allocating into the cache, or cacheable instruction fetches when there is no L2 cache.
ReadCleanNot used.
ReadSharedL1 Data linefills started by a load instruction, or L2 linefills started by an instruction fetch.
ReadUniqueL1 Data linefills started by a store instruction.
CleanUniqueStore instructions that hit in the cache but the line is not in a unique coherence state.
MakeUniqueStore instructions of a full cache line of data, that miss in the caches, and are allocating into the L2 cache.
CleanSharedCache maintenance instructions.
CleanInvalidCache maintenance instructions.
MakeInvalidCache maintenance instructions.
DVMOpTLB and instruction cache maintenance instructions.
EOBarrierDMB instructions.
ECBarrierDSB instructions. DVM sync snoops received from the interconnect.
WriteNoSnpPtlNon-cacheable store instructions.
WriteNoSnpFullNon-cacheable store instructions, or evictions of non-shareable cache lines from the L1 and L2 cache.
WriteUniqueFullCacheable writes of a full cache line, that are not allocating into L1 or L2 caches, for example streaming writes.
WriteUniquePtlCacheable writes of less than a full cache line that are not allocating into L1 or L2.
WriteBackFull Evictions of dirty lines from the L1 or L2 cache.
WriteBackPtlNot used.
WriteCleanFullEvictions of dirty lines from the L2 cache, when the line is still present in an L1 cache. Some cache maintenance instructions.
WriteCleanPtlNot used.
WriteEvictFullEvictions of unique clean lines, when configured in the L2ACTLR.
Evict Evictions of clean lines, when configured in the L2ACTLR.