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7.2. Snoop Control Unit

The Cortex-A53 processor supports between one and four individual cores with L1 Data cache coherency maintained by the SCU. The SCU is clocked synchronously and at the same frequency as the cores.

The SCU maintains coherency between the individual data caches in the processor using ACE modified equivalents of MOESI state, as described in Data Cache Unit.

The SCU contains buffers that can handle direct cache-to-cache transfers between cores without having to read or write any data to the external memory system. Cache line migration enables dirty cache lines to be moved between cores, and there is no requirement to write back transferred cache line data to the external memory system.

Each core has tag and dirty RAMs that contain the state of the cache line. Rather than access these for each snoop request the SCU contains a set of duplicate tags that permit each coherent data request to be checked against the contents of the other caches in the cluster. The duplicate tags filter coherent requests from the system so that the cores and system can function efficiently even with a high volume of snoops from the system.

When an external snoop hits in the duplicate tags a request is made to the appropriate core.