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3.2.8. AArch32 execution modes

ARMv7 and earlier versions of the ARM architecture define a set of named processor modes, including modes that correspond to different exception types. For compatibility, AArch32 state retains these processor modes.

Table 3.3 shows the AArch32 processor modes, and the Exception level of each mode.

Table 3.3. AArch32 processor modes and associated Exception levels
AArch32 processor modeEL3 usingSecurity stateException level
UserAArch32 or AArch64Non-secure or SecureEL0
System, FIQ, IRQ, AArch64Non-secure or SecureEL1
Supervisor, AArch32 Non-secureEL1
Abort, UndefinedAArch32SecureEL3
HypAArch32 or AArch64Non-secure onlyEL2
MonitorAArch32 Secure onlyEL3

When the EL3 using column of Table 3.3 shows:


The row refers to information shown in Figure 3.1.


The row refers to information shown in Figure 3.2.

A processor mode name does not indicate the current security state. To distinguish between a mode in Secure state and the equivalent mode in Non-secure state, the mode name is qualified as Secure or Non-secure. For example, a description of AArch32 operation in EL1 might reference the Secure FIQ mode, or to the Non-secure FIQ mode.