The CSSELR characteristics are:
- Purpose
Selects the current CCSIDR, see Cache Size ID Register, by specifying:
The required cache level.
The cache type, either instruction or data cache.
- Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW If the CSSELR level field is programmed to a cache level that is not implemented, then a read of CSSELR returns an unknown value in CSSELR.Level.
- Configurations
CSSELR (NS) is architecturally mapped to AArch64 register CSSELR_EL1. See Cache Size Selection Register.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
- Attributes
CSSELR is a 32-bit register.
Figure 4.94 shows the CSSELR bit assignments.
Table 4.195 shows the CSSELR bit assignments.
To access the CSSELR:
MRC p15, 2, <Rt>, c0, c0, 0; Read CSSELR into Rt MCR p15, 2, <Rt>, c0, c0, 0; Write Rt to CSSELR
Register access is encoded as follows: