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4.5.76. CPU Auxiliary Control Register

The CPUACTLR characteristics are:

Purpose

Provides implementation defined configuration and control options for the processor. There is one 64-bit CPU Auxiliary Control Register for each core in the cluster.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RWRWRWRWRW

The CPU Auxiliary Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE or ACP traffic begins.

Note

Setting many of these bits can cause significantly lower performance on your code. Therefore, it is suggested that you do not modify this register unless directed by Arm.

Configurations

CPUACTLR is:

Attributes

CPUACTLR is a 64-bit register.

Figure 4.140 shows the CPUACTLR bit assignments.

Figure 4.140. CPUACTLR bit assignments

Figure 4.140. CPUACTLR bit assignments

Table 4.254 shows the CPUACTLR bit assignments.

Table 4.254. CPUACTLR bit assignments
BitsNameFunction
[63:45]-Reserved, res0.
[44]ENDCCASCI

Enable data cache clean as data cache clean/invalidate. The possible values are:

0

Normal behavior, data cache clean operations are unaffected. This is the reset value.

1

Executes data cache clean operations as data cache clean and invalidate. The following operations are affected:

  • In AArch32, DCCSW is executed as DCCISW, DCCMVAU and DCCMVAC are executed as DCCIMVAC.

  • In AArch64, DC CSW is executed as DC CISW, DC CVAU and DC CVAC are executed as DC CIVAC.

[43:31-Reserved, res0.
[30]FPDIDIS

Disable floating-point dual issue. The possible values are:

0

Enable dual issue of floating-point, Advanced SIMD and Cryptography instructions. This is the reset value.

1

Disable dual issue of floating-point, Advanced SIMD and Cryptography instructions.

[29]DIDIS

Disable Dual Issue. The possible values are:

0

Enable Dual Issue of instructions. This is the reset value.

1

Disable Dual Issue of all instructions.

[28:27]RADIS

Write streaming no-allocate threshold. The possible values are:

0b00

16th consecutive streaming cache line does not allocate in the L1 or L2 cache.

0b01

128th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is the reset value.

0b10

512th consecutive streaming cache line does not allocate in the L1 or L2 cache.

0b11

Disables streaming. All write-allocate lines allocate in the L1 or L2 cache.

[26:25]L1RADIS

Write streaming no-L1-allocate threshold. The possible values are:

0b00

4th consecutive streaming cache line does not allocate in the L1 cache. This is the reset value.

0b01

64th consecutive streaming cache line does not allocate in the L1 cache.

0b10

128th consecutive streaming cache line does not allocate in the L1 cache.

0b11

Disables streaming. All write-allocate lines allocate in the L1 cache.

[24]DTAH

Disable Transient allocation hint. The possible values are:

0

Normal operation.

1

Transient and no-read-allocate hints in the MAIR are ignored and treated the same as non-transient, read-allocate types for loads. The LDNP instruction in AArch64 behaves the same as the equivalent LDP instruction. This is the reset value.

[23]STBPFRS

Disable ReadUnique request for prefetch streams initiated by STB accesses:

0

ReadUnique used for prefetch streams initiated from STB accesses. This is the reset value.

1

ReadShared used for prefetch streams initiated from STB accesses.

[22]STBPFDIS

Disable prefetch streams initiated from STB accesses:

0

Enable Prefetch streams initiated from STB accesses. This is the reset value.

1

Disable Prefetch streams initiated from STB accesses.

[21]IFUTHDIS

IFU fetch throttle disabled. The possible values are:

0

Fetch throttle enabled. This is the reset value.

1

Fetch throttle disabled. This setting increases power consumption.

[20:19]NPFSTRM

Number of independent data prefetch streams. The possible values are:

0b00

1 stream.

0b01

2 streams. This is the reset value.

0b10

3 streams.

0b11

4 streams.

[18]DSTDIS

Enable device split throttle. The possible values are:

0

Device split throttle disabled.

1

Device split throttle enabled. This is the reset value.

[17]STRIDE

Enable stride detection. The possible values are:

0

2 consecutive strides to trigger prefetch. This is the reset value.

1

3 consecutive strides to trigger prefetch.

[16]-Reserved, res0.
[15:13]L1PCTL

L1 Data prefetch control. The value of the this field determines the maximum number of outstanding data prefetches allowed in the L1 memory system, excluding those generated by software load or PLD instructions. The possible values are:

0b000

Prefetch disabled.

0b001

1 outstanding prefetch allowed.

0b010

2 outstanding prefetches allowed.

0b011

3 outstanding prefetches allowed.

0b100

4 outstanding prefetches allowed.

0b101

5 outstanding prefetches allowed. This is the reset value.

0b110

6 outstanding prefetches allowed.

0b111

8 outstanding prefetches allowed.

[12:11]-Reserved, res0.
[10] DODMBS

Disable optimized Data Memory Barrier behavior. The possible values are:

0

Enable optimized Data Memory Barrier behavior. This is the reset value.

1

Disable optimized Data Memory Barrier behavior.

[9:7]-Reserved, res0.
[6]L1DEIEN

L1 D-cache data RAM error injection enable. The possible values are;

0

Normal behavior, errors are not injected. This is the reset value.

1

Double-bit errors are injected on all writes to the L1 D-cache data RAMs for the first word of each 32-byte region.

[5:0]-Reserved, res0.

To access the CPUACTLR:

MRRC p15, 0, <Rt>, <Rt2>, c15; Read CPU Auxiliary Control Register
MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register
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