The CPUECTLR characteristics are:
Provides additional implementation defined configuration and control options for the processor.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
The CPUECTLR can be written dynamically.
The CPUECTLR is:
Architecturally mapped to the AArch64 CPUECTLR_EL1 register. See CPU Extended Control Register, EL1.
CPUECTLR is a 64-bit register.
Figure 4.141 shows the CPUECTLR bit assignments.
Table 4.255 shows the CPUECTLR bit assignments.
Enable hardware management of data coherency with other cores in the cluster. The possible values are:
Set the SMPEN bit before enabling the caches, even if there is only one core in the system.
Advanced SIMD and Floating-point retention control. The possible values are:
This field is present only if the Advanced SIMD and Floating-point Extension is implemented. Otherwise, it is res0.
CPU retention control. The possible values are:
Software must not rely on retention state entry when the system counter is in low-power modes where CNTVALUEB increments are greater than 1. Entry to retention state relies on the system counter increments being +1.
To access the CPUECTLR:
MRRC p15, 1, <Rt>, <Rt2>, c15; Read CPU Extended Control Register MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register