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4.5.55.  Data Fault Address Register

The DFAR characteristics are:

Purpose

Holds the virtual address of the faulting address that caused a synchronous Data Abort exception.

Usage constraints

This register is accessible as follows:

 

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

DFAR(S)---RW--RW
DFAR(NS)--RW-RWRW-
Configurations

DFAR (NS) is architecturally mapped to AArch64 register FAR_EL1[31:0]. See Fault Address Register, EL1.

DFAR (S) is architecturally mapped to AArch32 register HDFAR. See Hyp Data Fault Address Register.

DFAR (S) is architecturally mapped to AArch64 register FAR_EL2[31:0]. See Fault Address Register, EL2.

Attributes

DFAR is a 32-bit register.

Figure 4.126 shows the DFAR bit assignments.

Figure 4.126. DFAR bit assignments

Figure 4.126. DFAR bit assignments

Table 4.234 shows the DFAR bit assignments.

Table 4.234.  DFAR bit assignments
BitsNameFunction
[31:0]VA

The Virtual Address of faulting address of synchronous Data Abort exception


To access the DFAR:

MRC p15, 0, <Rt>, c6, c0, 0 ; Read DFAR into Rt
MCR p15, 0, <Rt>, c6, c0, 0 ; Write Rt to DFAR
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