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4.5.48. Data Fault Status Register

The DFSR characteristics are:

Purpose

Holds status information about the last data fault.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RWRWRWRWRW
Configurations

DFSR (NS) is architecturally mapped to AArch64 register ESR_EL1.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

There are two formats for this register. The current translation table format determines which format of the register is used.

Attributes

DFSR is a 32-bit register.

This section describes:

DFSR when using the Short-descriptor translation table format

Figure 4.121 shows the DFSR bit assignments when using the Short-descriptor translation table format.

Figure 4.121. DFSR bit assignments for Short-descriptor translation table format

Figure 4.121. DFSR bit assignments for Short-descriptor translation
table format

Table 4.226 shows the DFSR bit assignments when using the Short-descriptor translation table format.

Table 4.226. DFSR bit assignments for Short-descriptor translation table format
BitsNameFunction
[31:14]-

Reserved, res0.

[13]CM

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0

Abort not caused by a cache maintenance operation.

1

Abort caused by a cache maintenance operation.

[12]ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11]WnR

Write not Read bit. This field indicates whether the abort was caused by a write or a read access:

0

Abort caused by a read access.

1

Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

[10]FS[4]Part of the Fault Status field. See bits [3:0] in this table.
[9]-

RAZ.

[8]-

Reserved, res0.

[7:4]Domain

Specifies which of the 16 domains, D15-D0, was being accessed when a data fault occurred.

For permission faults that generate Data Abort exception, this field is unknown. Armv8 deprecates any use of the domain field in the DFSR.

[3:0]FS[3:0]

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved:

0b00001

Alignment fault.

0b00010

Debug event.

0b00011

Access flag fault, section.

0b00100

Instruction cache maintenance fault.

0b00101

Translation fault, section.

0b00110

Access flag fault, page.

0b00111

Translation fault, page.

0b01000

Synchronous external abort, non-translation.

0b01001

Domain fault, section.

0b01011

Domain fault, page.

0b01100

Synchronous external abort on translation table walk, first level.

0b01101

Permission fault, section.

0b01110

Synchronous external abort on translation table walk, second level.

0b01111

Permission fault, second level.

0b10000

TLB conflict abort.

0b10101

LDREX or STREX abort.

0b10110

Asynchronous external abort.

0b11000

Asynchronous parity error on memory access.

0b11001

Synchronous parity error on memory access.

0b11100

Synchronous parity error on translation table walk, first level.

0b11110

Synchronous parity error on translation table walk, second level.


DFSR when using the Long-descriptor translation table format

Figure 4.122 shows the DFSR bit assignments when using the Long-descriptor translation table format.

Figure 4.122. DFSR bit assignments for Long-descriptor translation table format

Figure 4.122. DFSR bit assignments for Long-descriptor translation
table format

Table 4.227 shows the DFSR bit assignments when using the Long-descriptor translation table format.

Table 4.227. DFSR bit assignments for Long-descriptor translation table format
BitsNameFunction
[31:14]-

Reserved, res0.

[13]CM

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0

Abort not caused by a cache maintenance operation.

1

Abort caused by a cache maintenance operation.

[12]ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11]WnR

Write not Read bit. This field indicates whether the abort was caused by a write or a read access:

0

Abort caused by a read access.

1

Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

[10]-Reserved, res0.
[9]-

RAO.

[8:6]-

Reserved, res0.

[5:0]Status

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.

0b000000

Address size fault in TTBR0 or TTBR1.

0b0001LL

Translation fault, LL bits indicate level.

0b0010LL

Access fault flag, LL bits indicate level.

0b0011LL

Permission fault, LL bits indicate level.

0b010000

Synchronous external abort.

0b010001

Asynchronous external abort.

0b0101LL

Synchronous external abort on translation table walk, LL bits indicate level.

0b011000

Synchronous parity error on memory access.

0b011001

Asynchronous parity error on memory access (DFSR only).

0b0111LL

Synchronous parity error on memory access on translation table walk, first level, LL bits indicate level.

0b100001

Alignment fault.

0b100010

Debug event.

0b110000

TLB conflict abort.

0b110101

LDREX or STREX abort.


Table 4.228 shows how the LL bits in the Status field encode the lookup level associated with the MMU fault.

Table 4.228. Encodings of LL bits associated with the MMU fault
BitsMeaning
0b00Reserved
0b01Level 1
0b10Level 2
0b11Level 3

To access the DFSR:

MRC p15, 0, <Rt>, c5, c0, 0; Read DFSR into Rt
MCR p15, 0, <Rt>, c5, c0, 0; Write Rt to DFSR
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