The ID_DFR0 characteristics are:
Provides top level information about the debug system in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with the Main ID Register, MIDR.
ID_DFR0 is architecturally mapped to AArch64 register ID_DFR0_EL1. See AArch32 Debug Feature Register 0.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_DFR0 is a 32-bit register.
Figure 4.81 shows the ID_DFR0 bit assignments.
Table 4.168 shows the ID_DFR0 bit assignments.
Indicates support for performance monitor model:
Indicates support for memory-mapped debug model for M profile processors:
Indicates support for memory-mapped trace model:
In the Trace registers, the ETMIDR gives more information about the implementation.
Indicates support for coprocessor-based trace model:
Indicates support for coprocessor-based Secure debug model:
Indicates support for coprocessor-based debug model:
To access the ID_DFR0:
MRC p15,0,<Rt>,c0,c1,2 ; Read ID_DFR0 into Rt
Register access is encoded as follows: