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4.5.45. Domain Access Control Register

The DACR characteristics are:

Purpose

Defines the access permission for each of the sixteen memory domains.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RWRWRWRWRW
Configurations

DACR (NS) is architecturally mapped to AArch64 register DACR32_EL2. See Domain Access Control Register.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

DACR has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.

DACR has no function when TTBCR.EAE is set to 1, to select the Long-descriptor translation table format.

Attributes

DACR is a 32-bit register.

Figure 4.119 shows the DACR bit assignments.

Figure 4.119. DACR bit assignments

Figure 4.119. DACR bit assignments

Table 4.224 shows the DACR bit assignments.

Table 4.224. DACR bit assignments
BitsNameFunction
[31:0]

D<n>, bits [2n+1:2n], for n = 0 to 15

Domain n access permission, where n = 0 to 15. Permitted values are:

0b00

No access. Any access to the domain generates a Domain fault.

0b01

Client. Accesses are checked against the permission bits in the translation tables.

0b11

Manager. Accesses are not checked against the permission bits in the translation tables.

The value 0b10 is reserved.


To access the DACR:

MRC p15, 0, <Rt>, c3, c0, 0 ; Read DACR into Rt
MCR p15, 0, <Rt>, c3, c0, 0 ; Write Rt to DACR
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