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4.5.37. Hyp Configuration Register 2

The HCR2 characteristics are:

Purpose

Provides additional configuration controls for virtualization.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

----RWRW-
Configurations

HCR2 is architecturally mapped to AArch64 register HCR_EL2[63:32].

This register is accessible only at EL2 or EL3.

Attributes

HCR2 is a 32-bit register.

Figure 4.108 shows the HCR2 bit assignments.

Figure 4.108. HCR2 bit assignments

Figure 4.108. HCR2 bit assignments

Table 4.213 shows the HCR2 bit assignments.

Table 4.213.  HCR2 bit assignments
BitsNameFunction
[31:2]-

Reserved, res0.

[1]ID

Stage 2 Instruction cache disable. When HCR.VM is 1, this forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regime. The possible values are:

0

No effect on the stage 2 of the EL1/EL0 translation regime for instruction accesses.

1

Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL0/EL1 translation regime.

[0]CD

Stage 2 Data cache disable. When HCR.VM is 1, this forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regime. The possible values are:

0

No effect on the stage 2 of the EL1/EL0 translation regime for data accesses and translation table walks.

1

Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL0/EL1 translation regime.


To access the HCR2:

MRC p15,4,<Rt>,c1,c1,4 ; Read HCR2 into Rt
MCR p15,4,<Rt>,c1,c1,4 ; Write Rt to HCR2
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