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4.5.57.  Hyp Data Fault Address Register

The HDFAR characteristics are:

Purpose

Holds the virtual address of the faulting address that caused a synchronous Data Abort exception that is taken to Hyp mode.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

---RWRW-

An execution in a Non-secure EL1 state, or in Secure state, makes the HDFAR unknown.

Configurations

HDFAR is architecturally mapped to AArch64 register FAR_EL2[31:0] when EL3 is AArch64. See Fault Address Register, EL2.

HDFAR (S) is architecturally mapped to AArch32 register DFAR (S). See Data Fault Address Register.

Attributes

HDFAR is a 32-bit register.

Figure 4.128 shows the HDFAR bit assignments.

Figure 4.128. HDFAR bit assignments

Figure 4.128. HDFAR bit assignments

Table 4.236 shows the HDFAR bit assignments.

Table 4.236.  HDFAR bit assignments
BitsNameFunction
[31:0]VA

The Virtual Address of faulting address of synchronous Data Abort exception


To access the HDFAR:

MRC p15, 4, <Rt>, c6, c0, 0 ; Read HDFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 0 ; Write Rt to HDFAR
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