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4.5.54. Hyp Syndrome Register

The HSR characteristics are:

Purpose

Holds syndrome information for an exception taken to Hyp mode.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

----RWRW-
Configurations

HSR is architecturally mapped to AArch64 register ESR_EL2. See Exception Syndrome Register, EL2.

This register is accessible only at EL2 or EL3.

Attributes

HSR is a 32-bit register.

Figure 4.125 shows the HSR bit assignments.

Figure 4.125. HSR bit assignments

Figure 4.125. HSR bit assignments

Table 4.233 shows the HSR bit assignments.

Table 4.233. HSR bit assignments
BitsNameFunction
[31:26]EC

Exception class. The exception class for the exception that is taken in Hyp mode. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

[25]IL

Instruction length. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

[24:0]ISS

Instruction specific syndrome. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information. The interpretation of this field depends on the value of the EC field. See Encoding of ISS[24:20] when HSR[31:30] is 0b00.


Encoding of ISS[24:20] when HSR[31:30] is 0b00

For EC values that are nonzero and have the two most-significant bits 0b00, ISS[24:20] provides the condition field for the trapped instruction, together with a valid flag for this field. The encoding of this part of the ISS field is:

CV, ISS[24]

Condition valid. Possible values of this bit are:

0

The COND field is not valid.

1

The COND field is valid.

When an instruction is trapped, CV is set to 1.

COND, ISS[23:20]

The Condition field for the trapped instruction. This field is valid only when CV is set to 1.

If CV is set to 0, this field is res0.

When an instruction is trapped, the COND field is set to the condition the instruction was executed with.

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