The HSR characteristics are:
Holds syndrome information for an exception taken to Hyp mode.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - - RW RW -
HSR is architecturally mapped to AArch64 register ESR_EL2. See Exception Syndrome Register, EL2.
This register is accessible only at EL2 or EL3.
HSR is a 32-bit register.
Figure 4.125 shows the HSR bit assignments.
Table 4.233 shows the HSR bit assignments.
Exception class. The exception class for the exception that is taken in Hyp mode. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Instruction length. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Instruction specific syndrome. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information. The interpretation of this field depends on the value of the EC field. See Encoding of ISS[24:20] when HSR[31:30] is 0b00.
For EC values that are nonzero and have the two most-significant bits 0b00, ISS[24:20] provides the condition field for the trapped instruction, together with a valid flag for this field. The encoding of this part of the ISS field is:
- CV, ISS
Condition valid. Possible values of this bit are:
The COND field is not valid.
The COND field is valid.
When an instruction is trapped, CV is set to 1.
- COND, ISS[23:20]
The Condition field for the trapped instruction. This field is valid only when CV is set to 1.
If CV is set to 0, this field is res0.
When an instruction is trapped, the COND field is set to the condition the instruction was executed with.