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4.5.43. Hyp Translation Control Register

The HTCR characteristics are:

Purpose

Controls translation table walks required for the stage 1 translation of memory accesses from Hyp mode, and holds cacheability and shareability information for the accesses.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

----RWRW-
Configurations

HTCR is architecturally mapped to AArch64 register TCR_EL2. See Translation Control Register, EL2.

Attributes

HTCR is a 32-bit register.

Figure 4.117 shows the HTCR bit assignments.

Figure 4.117. HTCR bit assignments

Figure 4.117. HTCR bit assignments

Table 4.222 shows the HTCR bit assignments.

Table 4.222.  HTCR bit assignments
BitsNameFunction
[31]-

Reserved, res1.

[30:24]-Reserved, res0.
[23]-

Reserved, res1.

[22:14]-Reserved, res0.
[13:12]SH0

Shareability attribute for memory associated with translation table walks using TTBR0. The possible values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer shareable.

0b11

Inner shareable.

[11:10]ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0. The possible values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8]IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0. The possible values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7:3]-

Reserved, res0.

[2:0]T0SZ

Size offset of the memory region addressed by TTBR0. The region size is 2(32-TSIZE) bytes.


The processor does not use the implementation-defined bit, HTCR[30], so this bit is res0.

To access the HTCR:

MRC p15, 4, <Rt>, c2, c0, 2; Read HTCR into Rt
MCR p15, 4, <Rt>, c2, c0, 2; Write Rt to HTCR
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