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4.5.14. Instruction Set Attribute Register 0

The ID_ISAR0 characteristics are:

Purpose

Provides information about the instruction sets implemented by the processor in AArch32.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO

Must be interpreted with ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5. See:

Configurations

ID_ISAR0 is architecturally mapped to AArch64 register ID_ISAR0_EL1. See AArch32 Instruction Set Attribute Register 0.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ID_ISAR0 is a 32-bit register.

Figure 4.86 shows the ID_ISAR0 bit assignments.

Figure 4.86. ID_ISAR0 bit assignments

Figure 4.86. ID_ISAR0 bit assignments

Table 4.178 shows the ID_ISAR0 bit assignments.

Table 4.178. ID_ISAR0 bit assignments
BitsNameFunction
[31:28]-

Reserved, res0.

[27:24]Divide

Indicates the implemented Divide instructions:

0x2
  • SDIV and UDIV in the T32 instruction set.

  • SDIV and UDIV in the A32 instruction set.

[23:20]Debug

Indicates the implemented Debug instructions:

0x1

BKPT.

[19:16]Coproc

Indicates the implemented Coprocessor instructions:

0x0

None implemented, except for separately attributed by the architecture including CP15, CP14, Advanced SIMD and Floating-point.

[15:12]CmpBranch

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:

0x1

CBNZ and CBZ.

[11:8]Bitfield

Indicates the implemented bit field instructions:

0x1

BFC, BFI, SBFX, and UBFX.

[7:4]BitCount

Indicates the implemented Bit Counting instructions:

0x1

CLZ.

[3:0]Swap

Indicates the implemented Swap instructions in the A32 instruction set:

0x0

None implemented.


To access the ID_ISAR0:

MRC p15, 0, <Rt>, c0, c2, 0 ; Read ID_ISAR0 into Rt

Register access is encoded as follows:

Table 4.179. ID_ISAR0 access encoding
coprocopc1CRnCRmopc2
111100000000010000

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