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4.5.15. Instruction Set Attribute Register 1

The ID_ISAR1 characteristics are:

Purpose

Provides information about the instruction sets implemented by the processor in AArch32.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO

Must be interpreted with ID_ISAR0, ID_ISAR2, ID_ISAR3, ID_ISAR4 and ID_ISAR5. See:

Configurations

ID_ISAR1 is architecturally mapped to AArch64 register ID_ISAR1_EL1. See AArch32 Instruction Set Attribute Register 1.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ID_ISAR1 is a 32-bit register.

Figure 4.87 shows the ID_ISAR1 bit assignments.

Figure 4.87. ID_ISAR1 bit assignments

Figure 4.87. ID_ISAR1 bit assignments

Table 4.180 shows the ID_ISAR1 bit assignments.

Table 4.180. ID_ISAR1 bit assignments
BitsNameFunction
[31:28]Jazelle

Indicates the implemented Jazelle state instructions:

0x1

The BXJ instruction, and the J bit in the PSR.

[27:24]Interwork

Indicates the implemented Interworking instructions:

0x3
  • The BX instruction, and the T bit in the PSR.

  • The BLX instruction. The PC loads have BX-like behavior.

  • Data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear, have BX-like behavior.

[23:20]Immediate

Indicates the implemented data-processing instructions with long immediates:

0x1
  • The MOVT instruction.

  • The MOV instruction encodings with zero-extended 16-bit immediates.

  • The T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates, and other ADD, ADR, and SUB encodings cross-referenced by the pseudocode for those encodings.

[19:16]IfThen

Indicates the implemented If-Then instructions in the T32 instruction set:

0x1

The IT instructions, and the IT bits in the PSRs.

[15:12]Extend

Indicates the implemented Extend instructions:

0x2
  • The SXTB, SXTH, UXTB, and UXTH instructions.

  • The SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions.

[11:8]Except_AR

Indicates the implemented A profile exception-handling instructions:

0x1

The SRS and RFE instructions, and the A profile forms of the CPS instruction.

[7:4]Except

Indicates the implemented exception-handling instructions in the A32 instruction set:

0x1

The LDM (exception return), LDM (user registers), and STM (user registers) instruction versions.

[3:0]Endian

Indicates the implemented Endian instructions:

0x1

The SETEND instruction, and the E bit in the PSRs.


To access the ID_ISAR1:

MRC p15, 0, <Rt>, c0, c2, 1 ; Read ID_ISAR1 into Rt

Register access is encoded as follows:

Table 4.181. ID_ISAR1 access encoding
coprocopc1CRnCRmopc2
111100000000010001

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