The ISR characteristics are:
Shows whether an IRQ, FIQ, or external abort is pending. An indicated pending abort might be a physical abort or a virtual abort.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
ISR is architecturally mapped to AArch64 register ISR_EL1. See Interrupt Status Register.
There is one copy of this register that is used in both Secure and Non-secure states.
ISR is a 32-bit register.
Figure 4.137 shows the ISR bit assignments.
Table 4.250 shows the ISR bit assignments.
External abort pending bit:
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
FIQ pending bit. Indicates whether an FIQ interrupt is pending:
To access the ISR:
MRC p15, 0, <Rt>, c12, c1, 1; Read ISR into Rt
Register access is encoded as follows: