You copied the Doc URL to your clipboard.

4.5.72. Interrupt Status Register

The ISR characteristics are:

Purpose

Shows whether an IRQ, FIQ, or external abort is pending. An indicated pending abort might be a physical abort or a virtual abort.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO
Configurations

ISR is architecturally mapped to AArch64 register ISR_EL1. See Interrupt Status Register.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ISR is a 32-bit register.

Figure 4.137 shows the ISR bit assignments.

Figure 4.137. ISR bit assignments

Figure 4.137. ISR bit assignments

Table 4.250 shows the ISR bit assignments.

Table 4.250. ISR bit assignments
BitsNameFunction
[31:9]-

Reserved, res0.

[8]A

External abort pending bit:

0

No pending external abort.

1

An external abort is pending.

[7]I

IRQ pending bit. Indicates whether an IRQ interrupt is pending:

0

No pending IRQ.

1

An IRQ interrupt is pending.

[6]F

FIQ pending bit. Indicates whether an FIQ interrupt is pending:

0

No pending FIQ.

1

An FIQ interrupt is pending.

[5:0]-

Reserved, res0.


To access the ISR:

MRC p15, 0, <Rt>, c12, c1, 1; Read ISR into Rt

Register access is encoded as follows:

Table 4.251. ISR access encoding
coprocopc1CRnCRmopc2
111100011000001000

Was this page helpful? Yes No