The L2ACTLR characteristics are:
Provides configuration and control options for the L2 memory system.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
You can write to this register only when the L2 memory system is idle. Arm recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI or ACP traffic has begun.
If the register must be modified after a powerup reset sequence, to idle the L2 memory system, you must take the following steps:
Disable the MMU from each core followed by an ISB to ensure the MMU disable operation is complete, then followed by a DSB to drain previous memory transactions.
Ensure that the system has no outstanding AC channel coherence requests to the Cortex-A53 processor.
Ensure that the system has no outstanding ACP requests to the Cortex-A53 processor.
When the L2 is idle, the processor can update the L2ACTLR followed by an
ISB. After the L2ACTLR is updated, the MMUs can be enabled and normal ACE and ACP traffic can resume.
There is one copy of this register that is used in both Secure and Non-secure states.
L2ACTLR is mapped to the AArch64 L2ACTLR_EL1 register. See L2 Auxiliary Control Register, EL1.
L2ACTLR is a 32-bit register.
Figure 4.139 shows the L2ACTLR bit assignments.
Table 4.253 shows the L2ACTLR bit assignments.
L2 Victim Control.
L2 cache data RAM error injection enable. The possible values are:
L2 cache tag RAM error injection enable. The possible values are:
|||Enable UniqueClean evictions with data|
Enables UniqueClean evictions with data. The possible values are:
|||Disable clean/evict push to external|
Disables clean/evict push to external. The possible values are:
To access the L2ACTLR:
MRC p15, 1, <Rt>, c15, c0, 0; Read L2ACTLR into Rt MCR p15, 1, <Rt>, c15, c0, 0; Write Rt to L2ACTLR