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4.5.61. L2 Control Register

The L2CTLR characteristics are:

Purpose

Provides implementation defined control options for the L2 memory system.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RWRWRWRWRW

Note

L2CTLR is writeable. However, all writes to this register are ignored.

Configurations

L2CTLR is architecturally mapped to the AArch64 L2CTLR_EL1 register. See Control Register.

There is one L2CTLR for the Cortex-A53 processor.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

L2CTLR is a 32-bit register.

Figure 4.131 shows the L2CTLR bit assignments.

Figure 4.131. L2CTLR bit assignments

Figure 4.131. L2CTLR bit assignments

Table 4.239 shows the L2CTLR bit assignments.

Table 4.239. L2CTLR bit assignments
BitsNameFunction
[31:26]-

Reserved, res0.

[25:24]Number of cores

Number of cores present:

0b00

One core, core 0.

0b01

Two cores, core 0 and core 1.

0b10

Three cores, cores 0 to 2.

0b11

Four cores, cores 0 to 3.

These bits are read-only and the value of this field is set to the number of cores present in the configuration.

[23]-Reserved, RAZ
[22]CPU Cache Protection

CPU Cache Protection. Core RAMs are implemented:

0

Without ECC.

1

With ECC.

This field is RO.

[21]SCU-L2 Cache Protection

SCU-L2 Cache Protection. L2 cache is implemented:

0

Without ECC.

1

With ECC.

This field is RO.

[20:6]-

Reserved, RAZ.

[5]Data RAM input latency

L2 data RAM input latency

0

1-cycle input delay from L2 data RAMs.

1

2-cycle input delay from L2 data RAMs.

This field is RO.

[4:1]-Reserved, RAZ.
[0]Data RAM output latency

L2 data RAM output latency:

0

2-cycle output delay from L2 data RAMs.

1

3-cycle output delay from L2 data RAMs.

This field is RO.


To access the L2CTLR:

MRC p15, 1, <Rt>, c9, c0, 2; Read L2CTLR into Rt
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