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4.5.62. L2 Extended Control Register

The L2ECTLR characteristics are:

Purpose

Provides additional implementation defined control options for the L2 memory system. This register is used for dynamically changing, but implementation specific, control bits.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RWRWRWRWRW

The L2ECTLR can be written dynamically.

Configurations

L2ECTLR is architecturally mapped o the AArch64 L2ECTLR_EL1 register. See L2 Extended Control Register.

There is one copy of this register that is used in both Secure and Non-secure states.

There is one L2ECTLR for the Cortex-A53 processor.

Attributes

L2ECTLR is a 32-bit register.

Figure 4.132 shows the L2ECTLR bit assignments.

Figure 4.132. L2ECTLR bit assignments

Figure 4.132. L2ECTLR bit assignments

Table 4.240 shows the L2ECTLR bit assignments.

Table 4.240. L2ECTLR bit assignments
BitsNameFunction
[31]-

Reserved, res0.

[30]L2 internal asynchronous error

L2 internal asynchronous error caused by L2 RAM double-bit ECC error. The possible values are:

0

No pending asynchronous error. This is the reset value.

1

An asynchronous error has occurred.

A write of 0 clears this bit. A write of 1 is ignored.

[29]AXI or CHI asynchronous error

AXI or CHI asynchronous error indication. The possible values are:

0

No pending asynchronous error.

1

An asynchronous error has occurred.

A write of 0 clears this bit. A write of 1 is ignored.

[28:3]-

Reserved, res0.

[2:0]L2 dynamic retention control

L2 dynamic retention control. The possible values are:

0b000

L2 dynamic retention disabled. This is the reset value.

0b001

2 Generic Timer ticks required before retention entry.

0b010

8 Generic Timer ticks required before retention entry.

0b011

32 Generic Timer ticks required before retention entry.

0b100

64 Generic Timer ticks required before retention entry.

0b101

128 Generic Timer ticks required before retention entry.

0b110

256 Generic Timer ticks required before retention entry.

0b111

512 Generic Timer ticks required before retention entry.


To access the L2ECTLR:

MRC p15, 1, <Rt>, c9, c0, 3; Read L2ECTLR into Rt
MCR p15, 1, <Rt>, c9, c0, 3; Write Rt to L2ECTLR 
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