The MIDR characteristics are:
- Purpose
Provides identification information for the processor, including an implementer code for the device and a device ID number.
- Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO - Configurations
The MIDR is:
Architecturally mapped to the AArch64 MIDR_EL1 register. See Main ID Register, EL1.
Architecturally mapped to external MIDR_EL1 register.
- Attributes
MIDR is a 32-bit register.
Figure 4.76 shows the MIDR bit assignments.
Table 4.158 shows the MIDR bit assignments.
| Bits | Name | Function |
|---|---|---|
| [31:24] | Implementer | Indicates the implementer code. This value is:
|
| [23:20] | Variant | Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status. This value is:
|
| [19:16] | Architecture | Indicates the architecture code. This value is:
|
| [15:4] | PartNum | Indicates the primary part number. This value is:
|
| [3:0] | Revision | Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status. This value is:
|
To access the MIDR:
MRC p15, 0, <Rt>, c0, c0, 0; Read MIDR into Rt
Register access is encoded as follows:
The MIDR can be accessed through the external debug interface, offset 0xD00.