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4.5.13. Memory Model Feature Register 3

The ID_MMFR3 characteristics are:

Purpose

Provides information about the memory model and memory management support in AArch32.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO

Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR2. See:

Configurations

ID_MMFR3 is architecturally mapped to AArch64 register ID_MMFR3_EL1. See AArch32 Memory Model Feature Register 3.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ID_MMFR3 is a 32-bit register.

Figure 4.85 shows the ID_MMFR3 bit assignments.

Figure 4.85. ID_MMFR3 bit assignments

Figure 4.85. ID_MMFR3 bit assignments

Table 4.176 shows the ID_MMFR3 bit assignments.

Table 4.176. ID_MMFR3 bit assignments
BitsNameFunction
[31:28]Supersec

Supersections. Indicates support for supersections:

0x0

Supersections supported.

[27:24]CMemSz

Cached Memory Size. Indicates the size of physical memory supported by the processor caches:

0x2

1TByte, corresponding to a 40-bit physical address range.

[23:20]CohWalk

Coherent walk. Indicates whether translation table updates require a clean to the point of unification:

0x1

Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.

[19:16]-

Reserved, res0.

[15:12]MaintBcst

Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are broadcast:

0x2

Cache, TLB and branch predictor operations affect structures according to shareability and defined behavior of instructions.

[11:8]BPMaint

Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.

0x2

Supported branch predictor maintenance operations are:

  • Invalidate all branch predictors.

  • Invalidate branch predictors by MVA.

[7:4]CMaintSW

Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.

0x1

Supported hierarchical cache maintenance operations by set/way are:

  • Invalidate data cache by set/way.

  • Clean data cache by set/way.

  • Clean and invalidate data cache by set/way.

[3:0]CMaintVA

Cache maintenance by MVA. Indicates the supported cache maintenance operations by MVA.

0x1

Supported hierarchical cache maintenance operations by MVA are:

  • Invalidate data cache by MVA.[a]

  • Clean data cache by MVA.

  • Clean and invalidate data cache by MVA.

  • Invalidate instruction cache by MVA.

  • Invalidate all instruction cache entries.

[a] Invalidate data cache by MVA operations are treated as clean and invalidate data cache by MVA operations on the executing core. If the operation is broadcast to another core then it is broadcast as an invalidate data cache by MVA operation.


To access the ID_MMFR3:

MRC p15, 0, <Rt>, c0, c1, 7; Read ID_MMFR3 into Rt

Register access is encoded as follows:

Table 4.177. ID_MMFR3 access encoding
coprocopc1CRnCRmopc2
111100000000001111

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