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4.5.2. Multiprocessor Affinity Register

The MPIDR characteristics are:

Purpose

Provides an additional core identification mechanism for scheduling purposes in a cluster.

EDDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO
Configurations

The MPIDR is:

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

MPIDR is a 32-bit register.

Figure 4.77 shows the MPIDR bit assignments.

Figure 4.77. MPIDR bit assignments

Figure 4.77. MPIDR bit assignments

Table 4.160 shows the MPIDR bit assignments.

Table 4.160. MPIDR bit assignments
BitsNameFunction
[31]M

res1.

[30]U

Indicates a single core system, as distinct from core 0 in a cluster. This value is:

0

Core is part of a cluster.

[29:25]-

Reserved, res0.

[24]MT

Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:

0

Performance of cores at the lowest affinity level is largely independent.

[23:16] Aff2

Affinity level 2. Second highest level affinity field.

Indicates the value read in the CLUSTERIDAFF2 configuration signal.

[15:8] Aff1

Affinity level 1. Third highest level affinity field.

Indicates the value read in the CLUSTERIDAFF1 configuration signal.

[7:0]Aff0

Affinity level 0. Lowest level affinity field.

Indicates the core number in the Cortex-A53 processor. The possible values are:

0x0

A processor with one core only.

0x0, 0x1

A cluster with two cores.

0x0, 0x1, 0x2

A cluster with three cores.

0x0, 0x1, 0x2, 0x3

A cluster with four cores.


To access the MPIDR:

MRC p15,0,<Rt>,c0,c0,5 ; Read MPIDR into Rt

Register access is encoded as follows:

Table 4.161. MPIDR access encoding
coprocopc1CRnCRmopc2
111100000000000101

The EDDEVAFF0 can be accessed through the external debug interface, offset 0xFA8.

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