The NMRR characteristics are:
Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
The register is:
Used in conjunction with the PRRR.
Not accessible when using the Long-descriptor translation table format.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
The Non-secure NMRR is architecturally mapped to the AArch64 MAIR_EL1[63:32] register when TTBCR.EAE==0.
The Secure NMRR is mapped to the AArch64 MAIR_EL3[63:32] register when TTBCR.EAE==0.
NMRR has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.
NMRR is a 32-bit register when TTBCR.EAE is 0.
Figure 4.135 shows the NMRR bit assignments.
Table 4.247 shows the NMRR bit assignments.
Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TRn entry. n is the value of the TEX, C and B bits, see Table 4.242. The possible values of this field are:
Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal Memory by the PRRR.TRn entry. n is the value of the TEX, C and B bits, see Table 4.242. The possible values of this field are the same as those given for the ORn field.
[a] Where n is 0-7.
To access the NMRR:
MRC p15, 0, <Rt>, c10, c2, 1 ; Read NMRR into Rt MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to NMRR