The ID_PFR0 characteristics are:
Gives top-level information about the instruction sets supported by the processor in AArch32.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
ID_PFR0 must be interpreted with ID_PFR1.
ID_PFR0 is architecturally mapped to AArch64 register ID_PFR0_EL1. See AArch32 Processor Feature Register 0.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_PFR0 is a 32-bit register.
Figure 4.79 shows the ID_PFR0 bit assignments.
Table 4.164 shows the ID_PFR0 bit assignments.
Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:
Indicates support for Jazelle. This value is:
Indicates support for T32 instruction set. This value is:
Indicates support for A32 instruction set. This value is:
To access the ID_PFR0:
MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt
Register access is encoded as follows: