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4.5.6. Processor Feature Register 0

The ID_PFR0 characteristics are:

Purpose

Gives top-level information about the instruction sets supported by the processor in AArch32.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RORORORORO

ID_PFR0 must be interpreted with ID_PFR1.

Configurations

ID_PFR0 is architecturally mapped to AArch64 register ID_PFR0_EL1. See AArch32 Processor Feature Register 0.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

ID_PFR0 is a 32-bit register.

Figure 4.79 shows the ID_PFR0 bit assignments.

Figure 4.79. ID_PFR0 bit assignments

Figure 4.79. ID_PFR0 bit assignments

Table 4.164 shows the ID_PFR0 bit assignments.

Table 4.164. ID_PFR0 bit assignments
BitsNameFunction
[31:16]-

Reserved, res0.

[15:12]State3

Indicates support for Thumb Execution Environment (T32EE) instruction set. This value is:

0x0

Processor does not support the T32EE instruction set.

[11:8]State2

Indicates support for Jazelle. This value is:

0x1

Processor supports trivial implementation of Jazelle.

[7:4]State1

Indicates support for T32 instruction set. This value is:

0x3

Processor supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit T32 basic instructions.

[3:0]State0

Indicates support for A32 instruction set. This value is:

0x1

A32 instruction set implemented.


To access the ID_PFR0:

MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt

Register access is encoded as follows:

Table 4.165. ID_PFR0 access encoding
coprocopc1CRnCRmopc2
111100000000001000

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