The ID_PFR1 characteristics are:
Provides information about the programmers model and architecture extensions supported by the processor.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_PFR0.
ID_PFR1 is architecturally mapped to AArch64 register ID_PFR1_EL1. See AArch32 Processor Feature Register 1.
There is one copy of this register that is used in both Secure and Non-secure states.
ID_PFR1 is a 32-bit register.
Figure 4.80 shows the ID_PFR1 bit assignments.
Table 4.166 shows the ID_PFR1 bit assignments.
GIC CPU support:
Generic Timer support:
Indicates support for Virtualization:
M profile programmers' model support:
Indicates support for the standard programmers model for Armv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:
To access the ID_PFR1:
MRC p15,0,<Rt>,c0,c1,1 ; Read ID_PFR1 into Rt
Register access is encoded as follows: